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Cypress Semiconductor /psoc63 /BLE /BLELL /POC_REG__TIM_CONTROL

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Interpret as POC_REG__TIM_CONTROL

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0BB_CLK_FREQ_MINUS_1 0START_SLOT_OFFSET

Description

BLE Time Control

Fields

BB_CLK_FREQ_MINUS_1

LLH clock configuration. The clock frequency of the clock input to this design is configured in this register. This is used to derive a 1MHz clock.
START_SLOT_OFFSET

LLH clock configuration. The start of slot signal is offset by this value. If value is 0, the start of slot signal is generated at the 625us. The offset value is in terms of us.

Links

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Register License

Copyright 2016-2018 Cypress Semiconductor Corporation \n Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License.
You may obtain a copy of the License at \n
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and
limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data